ASIC Design and Verification

Units: 3

Digital systems design in CMOS VLSI technology: CMOS devise physics, fabrication, primitive components, design and layout methodology, integrated system architectures, timing, testing future trends of VLSI technology.

Offered in Spring Only

Units: 3

Design of digital application specific integrated circuits [ASICs] and Field Programmable Gate Arrays [FPGAs] based on hardware description languages [Verilog] and CAD tools. Emphasis on design practices and underlying methods. Introduction to ASIC specific design issues including verification, design for test, low power design and interfacing with memories. Required design project. Expected Prior Experience or Background: ECE 310 is useful but not assumed. Functionally, I assume that students are familiar with logic design, including combinational logic gates, sequential logic gates, timing design, Finite State Machines, etc.

Offered in Fall Only

Units: 3

Study of transaction-level modeling of digital systems-on-chip using SystemC. Simulation and analysis of performance in systems with distributed control. Synthesis of digital hardware from high-level descriptions. Physical design methodologies, including placement, routing, clock-tree insertion, timing, and power analysis. Significant project to design a core at system and physical levels. Knowledge of object-oriented programming with C and register-transfer-level design with verilog or VHDL is required.

Offered in Fall Only

Units: 3

This course covers the verification process used in validating the functional correctness in today's complex ASICs [application specific integrated circuits]. Topics include the fundamentals of simulation based functional verification, stimulus generation, results checking, coverage, debug, and formal verification. Provides the students with real world verification problems to allow them to apply what they learn.

Offered in Spring Only

Units: 3

The Universal Verification Methodology is the industry standard for functional verification of today's complex ASICs and FPGAs. Students will learn the content and use of UVM to architect and implement complex test benches. The characteristics and architecture of reusable verification components is a major focus of the course. Students will learn and implement verification components which are reusable across projects, from block level simulation to chip level simulation, and from simulation to emulation. The course projects teach and demonstrate advanced verification methodologies that prepare students for careers in functional verification of digital semiconductors.

Offered in Fall Only